1. Field of the Invention
The present invention is in the field of manufacturing LSI MOS field effect transistors wherein the gate electrode is used as an implantation mask and a silicate glass layer is applied as a gate edge masking for the ion implantation.
2. Description of the Prior Art
MOS processes in VLSI (very large scale integration) technology are employed in order to manufacture components with high packing density and high switching speeds. In addition to parasitic line capacitances, parasitic capacitors in the transistors themselves play a large part since they represent a limit for the gate transit times which can be obtained. The lateral outward diffusion of the highly doped source/drain regions into regions below the transistor gate leads to a significant increase of the so-called Miller capacitance between gate and diffusion regions.
The under-diffusion of the MOS transistor gate may be possibly prevented by a pullback of the implantation edge from the edge of the gate. A method of this type is disclosed in German Patent Application No. P 33 14 450.8 (corresponding to U.S. Ser. No. 589,639, filed Mar. 14, 1984 and assigned to the same assignee as the present application). In this application, a spacer oxide is formed by re-oxidation of a polysilicon gate before the source/drain implantation. The temperatures required are about 900.degree. C. and above, and an oxidation time of about 2 to 3 hours. This exposure to high temperatures is harmful to the component structures that have already been produced.
A further method wherein a space between the gate and the edge of the source/drain ion implantation is provided by means of an oxide layer at the sidewalls of the transistor gate is described in an article by Tsang et al in IEEE Trans. Electr. Dev. ED-29 (1982), pages 590 through 596. This article describes a fabrication process for lightly doped source/drain field effect transistors using SiO.sub.2 sidewall spacers. In this method, the deposited spacer oxide layers must be anisotropically etched before the source/drain implantation.
Another method for the reduction of diffusion under the gate area of MOS transistors is known from an article by Ogura et al (IEEE Trans. Electr. Dev. ED-27 (August 1980), pages 1359-1367). In this process, the source/drain implantation is carried out by means of using a polysilicon gate electrode as the mask. The polysilicon gate is subsequently over-etched. Such etching processes are critical production steps in VLSI technology and are to be avoided insofar as possible.